1. Field of the Invention
The present invention concerns, in general, the field of integrated circuits and more particularly a method of manufacturing a field effect transistor having an isolated gate, the gate formed of a semiconductor material combined locally with a metal. The present invention also concerns the transistor obtained by this method.
2. Background of the Invention
Generally, it is desired to manufacture integrated circuits having higher and higher densities and therefore transistors that are smaller and smaller. However, reducing the gate size of MOS transistors causes diverse parasitic effects. Among these effects, the short channel effect (SCE) and drain induced barrier lowering (DIBL) could be mentioned. The short channel effect is caused by the electrostatic influence of source and drain regions which are closest together when the gate length is reduced. The barrier lowering effect reduces the energy barrier for carriers (electrons and holes) in the channel while the MOS transistor is off, which increases leakage current. These two effects lower the threshold voltage (VT) in the case of a MOS transistor having an N channel or increase the threshold voltage in the case of a MOS transistor having a P channel. To maintain a satisfactory threshold voltage VT when the gate length is reduced, it is therefore necessary to modify the structure of the MOS transistor to at least partially cancel the short channel effect and barrier lowering.
To avoid parasitic problems of short channel and barrier lowering, non-published European patent application No 05/292650.8 filed 13 Dec. 2005 proposes a MOS transistor in which the gate is formed of a number of zones, as illustrated in FIG. 1. This MOS transistor is formed on a substrate 10. It comprises a gate G, a source S and a drain D. Spacers 14 are formed on each side of the gate G. The gate region G is isolated from the substrate 10 by a silicon oxide layer 16 referred to as the gate oxide. The gate G, positioned above the gate oxide layer 16, is composed of two zones. The first zone 18, positioned in the center of the gate length and close to the gate oxide 16, is of polycrystalline silicon. On each side of this polycrystalline silicon zone 18, and above it, the gate is silicided. The silicided zone 20, in contact with the gate oxide 16, allows a threshold voltage to be obtained which is higher on each side of the gate, lengthwise in the gate, while the threshold voltage corresponding to the polycrystalline silicon zone 18 situated in the center of the gate is lower. This increase in the threshold voltage on each side of the gate allows the reduction in the threshold voltage caused by the parasitic effects mentioned above to be cancelled at least partially.
The method proposed in this prior art for forming a gate comprising a silicided zone above and on each side of a polycrystalline silicon zone positioned in a central part of a gate is not easily controllable.